git.openwrt.org Git - openwrt/openwrt.git/blob

   1 From e0758a8694fbaffdc72940774db295585e951119 Mon Sep 17 00:00:00 2001
   2 From: Lorenzo Bianconi <lorenzo@kernel.org>
   3 Date: Fri, 28 Feb 2025 11:54:11 +0100
   4 Subject: [PATCH 03/15] net: airoha: Move reg/write utility routines in
   5  airoha_eth.h
   6
   7 This is a preliminary patch to introduce flowtable hw offloading
   8 support for airoha_eth driver.
   9
  10 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  11 Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  12 ---
  13  drivers/net/ethernet/airoha/airoha_eth.c | 28 +++---------------------
  14  drivers/net/ethernet/airoha/airoha_eth.h | 26 ++++++++++++++++++++++
  15  2 files changed, 29 insertions(+), 25 deletions(-)
  16
  17 --- a/drivers/net/ethernet/airoha/airoha_eth.c
  18 +++ b/drivers/net/ethernet/airoha/airoha_eth.c
  19 @@ -673,17 +673,17 @@ struct airoha_qdma_fwd_desc {
  20         __le32 rsv1;
  21  };
  22
  23 -static u32 airoha_rr(void __iomem *base, u32 offset)
  24 +u32 airoha_rr(void __iomem *base, u32 offset)
  25  {
  26         return readl(base + offset);
  27  }
  28
  29 -static void airoha_wr(void __iomem *base, u32 offset, u32 val)
  30 +void airoha_wr(void __iomem *base, u32 offset, u32 val)
  31  {
  32         writel(val, base + offset);
  33  }
  34
  35 -static u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val)
  36 +u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val)
  37  {
  38         val |= (airoha_rr(base, offset) & ~mask);
  39         airoha_wr(base, offset, val);
  40 @@ -691,28 +691,6 @@ static u32 airoha_rmw(void __iomem *base
  41         return val;
  42  }
  43
  44 -#define airoha_fe_rr(eth, offset)                              \
  45 -       airoha_rr((eth)->fe_regs, (offset))
  46 -#define airoha_fe_wr(eth, offset, val)                         \
  47 -       airoha_wr((eth)->fe_regs, (offset), (val))
  48 -#define airoha_fe_rmw(eth, offset, mask, val)                  \
  49 -       airoha_rmw((eth)->fe_regs, (offset), (mask), (val))
  50 -#define airoha_fe_set(eth, offset, val)                                \
  51 -       airoha_rmw((eth)->fe_regs, (offset), 0, (val))
  52 -#define airoha_fe_clear(eth, offset, val)                      \
  53 -       airoha_rmw((eth)->fe_regs, (offset), (val), 0)
  54 -
  55 -#define airoha_qdma_rr(qdma, offset)                           \
  56 -       airoha_rr((qdma)->regs, (offset))
  57 -#define airoha_qdma_wr(qdma, offset, val)                      \
  58 -       airoha_wr((qdma)->regs, (offset), (val))
  59 -#define airoha_qdma_rmw(qdma, offset, mask, val)               \
  60 -       airoha_rmw((qdma)->regs, (offset), (mask), (val))
  61 -#define airoha_qdma_set(qdma, offset, val)                     \
  62 -       airoha_rmw((qdma)->regs, (offset), 0, (val))
  63 -#define airoha_qdma_clear(qdma, offset, val)                   \
  64 -       airoha_rmw((qdma)->regs, (offset), (val), 0)
  65 -
  66  static void airoha_qdma_set_irqmask(struct airoha_qdma *qdma, int index,
  67                                     u32 clear, u32 set)
  68  {
  69 --- a/drivers/net/ethernet/airoha/airoha_eth.h
  70 +++ b/drivers/net/ethernet/airoha/airoha_eth.h
  71 @@ -248,4 +248,30 @@ struct airoha_eth {
  72         struct airoha_gdm_port *ports[AIROHA_MAX_NUM_GDM_PORTS];
  73  };
  74
  75 +u32 airoha_rr(void __iomem *base, u32 offset);
  76 +void airoha_wr(void __iomem *base, u32 offset, u32 val);
  77 +u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val);
  78 +
  79 +#define airoha_fe_rr(eth, offset)                              \
  80 +       airoha_rr((eth)->fe_regs, (offset))
  81 +#define airoha_fe_wr(eth, offset, val)                         \
  82 +       airoha_wr((eth)->fe_regs, (offset), (val))
  83 +#define airoha_fe_rmw(eth, offset, mask, val)                  \
  84 +       airoha_rmw((eth)->fe_regs, (offset), (mask), (val))
  85 +#define airoha_fe_set(eth, offset, val)                                \
  86 +       airoha_rmw((eth)->fe_regs, (offset), 0, (val))
  87 +#define airoha_fe_clear(eth, offset, val)                      \
  88 +       airoha_rmw((eth)->fe_regs, (offset), (val), 0)
  89 +
  90 +#define airoha_qdma_rr(qdma, offset)                           \
  91 +       airoha_rr((qdma)->regs, (offset))
  92 +#define airoha_qdma_wr(qdma, offset, val)                      \
  93 +       airoha_wr((qdma)->regs, (offset), (val))
  94 +#define airoha_qdma_rmw(qdma, offset, mask, val)               \
  95 +       airoha_rmw((qdma)->regs, (offset), (mask), (val))
  96 +#define airoha_qdma_set(qdma, offset, val)                     \
  97 +       airoha_rmw((qdma)->regs, (offset), 0, (val))
  98 +#define airoha_qdma_clear(qdma, offset, val)                   \
  99 +       airoha_rmw((qdma)->regs, (offset), (val), 0)
 100 +
 101  #endif /* AIROHA_ETH_H */